In modern integrated circuits, which also include high-voltage transistors, various circuit blocks are operated at different voltage levels. For example, the gate control of high-voltage transistors can take place by means of low-voltage components. The voltage supply of the individual circuit blocks must in this case take place in a controlled way during the operating state. The electrically isolated high-voltage transistors in the substrate are in a cut-off state when the gate electrode is at the same potential as the transistor body, and therefore are not suitable for energizing the affected part of the circuit. Therefore, one seeks a possibility of energizing circuit blocks of an integrated circuit comprising low-voltage transistors and high-voltage transistors at different voltage levels. For this one in particular needs a high-voltage transistor component that is in the conducting state without gate-source bias.
DE 10 2004 009 521 A1 describes a high-voltage PMOS transistor, which has a gate electrode, p-source in an n-well, p-drain in a p-well arranged within the n-well, and a field oxide region between the gate electrode and drain. The n-well is not as deep under the drain as it is under the source, and the depth of the p-well is the greatest under the drain.